CSC 342 Homework Assignment 2

CSC 342 Homework Assignment 2

A microprocessor scans the status of an output I/O device every 20ms. This is accomplished by means of a timer alerting the processor every 20ms. The interface of the device includes two ports: one for status and one for data output. How long does it take to scan and service the device given a clocking rate of 8MHz? Assume for simplicity that all pertinent instruction cycles take 12 clock cycles.

7.9 A particular system is controlled by an operator through commands entered from a keyboard. The average number of commands entered in an 8-hour interval is 60.

7.10 Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8KB/s on a continuous basis.

84% of the time the processor is being consumed.

b. Now assume that the device has two 16-byte buffers and interrupts the processor when one of the buffers is full. Naturally, interrupt processing takes longer, because the ISR must transfer 16 bytes. While executing the ISR, the processor takes about 8 microseconds for the transfer of each byte. Determine what fraction of processor time is consumed by this I/O device in this case.

7.12 A DMA module is transferring characters to memory using cycle stealing, from a device transmitting at 9600 bps. The processor is fetching instructions at the rate of 1 million instructions per second (1 MIPS). By how much will the processor be slowed down due to the DMA activity?

7.13 Consider a system in which bus cycles takes 500ns. Transfer of the bus control in either direction, from processor to I/O device or vice versa, takes 250 ns. One of the I/O devices has a data transfer rate of 50KB/s and employs DMA. Data are transferred 1 byte at a time.

a. Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus mastership prior to the start of a block transfer and maintains control of the bus until the whole block is transferred. For how long would the device tie up the bus when transferring a block of 128 bytes?

12.4 Many processors provide logic for performing arithmetic on packed decimal numbers. Although the rules for decimal arithmetic are similar to those for binary operations, the decimal results may require some corrections to the individual digits if binary logic is used. Consider the decimal addition of two unsigned numbers. If each number consists of N digits, then there are 4N bits in each number. The two numbers are to be added using a binary adder. Suggest a simple rule for correcting the result. Perform addition in this fashion on the numbers 1698 and 1786.

12.5 The tens complement of the decimal number X is defined to be 10^N – X, where N is the number of decimal digits in the number. Describe the use of ten’s complement representation to perform decimal subtraction. Illustrate the procedure by subtracting (0326)(base10) from (0736)(base10).

12.7 Consider a hypothetical computer with an instruction set of only two n-bit instructions. The first bit specifies the opcode, and the remaining bits specify one of the 2^(n-1) n-bit words of main memory. The two instructions are as follows:

12.8 Many instruction sets contain the instructions NOOP, meaning no operation, which has no effect on the processor state other than incrementing the program counter. Suggest some uses of this instruction.

12.12 The x86 architecture includes an instruction called Decimal Adjust after Addition (DAA). DAA performs the following sequence of instructions: